Learning Verilog for FPGA Development

Learn the fundamentals of Verilog, a popular and concise hardware description language used to create FPGA-based embedded systems.

FPGA development requires a big switch from more typical programming processes. In order to get an FPGA-based embedded system up and running, developers must add a hardware description language to their repertoire. In this course, Eduardo Corpeño helps you learn the fundamentals of one such language: the popular and concise Verilog. Eduardo begins with the basics; he explains what a hardware description language is and some similarities to traditional programming languages. He then covers the basic syntax of Verilog, as well as how to create test bench modules to run simulations, use variables with operators as an advantage of the behavioral level of abstraction, and more. Along the way, he provides demos and programming challenges that allow you to put your new skills to the test.

Introduction

• Verilog: Your key to digital design
• What you should know
• Setting up your environment

1. Hardware Description

• Hardware description languages
• Digital systems
• Levels of abstraction
• Gate level
• Register-transfer level

2. Basic Verilog Syntax

• Verilog modules
• Instantiating modules
• Gates and primitives
• Registers and wires
• Range specification
• Numbers and constants
• Always blocks
• The if-else statement
• Case statements
• Boolean algebra expressions
• Continuous assignments
• Blocking assignments
• Nonblocking assignments
• Challenge: From schematic to code
• Solution: From schematic to code

3. Simulation

• Simulation basics
• Test bench modules
• Stimulus variables
• Clock generation
• Initial and always blocks
• A simple simulation
• Timing directives
• Display tasks
• Challenge: You run the show
• Solution: You run the show

4. Combinational Systems

• Arithmetic and logic operators
• Challenge: Make a 4-bit arithmetic logic unit (ALU)
• Solution: Make a 4-bit arithmetic logic unit (ALU)
• Getting your ALU on a field-programmable gate array (FPGA)
• A functional demo of the ALU

5. Sequential Systems

• Flip-flops
• Edge sensitivity
• A shift register example
• Challenge: Make a clock divider
• Solution: Make a clock divider
• Getting your clock divider on an FPGA
• A functional demo of the clock divider

Conclusion

• Next steps